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The common problems in high speed PCB design and Solutions
   Edit:管理员   Browse:718  Date:2015-12-10 

With the more and more high, the operating frequency of the device, signal integrity problems faced by the high speed PCB design become a bottleneck of traditional design, engineers in the design of a complete solution is facing more and more challenges. Although the high-speed interconnect simulation tools and tools can help the designer solve some of the problems, in-depth exchanges continue to accumulate and industry but in high speed PCB design also needs to experience the.

There is a list of some of the problems of wide concern.

Effect of wiring topology on signal integrity

When the signal in the high-speed PCB board along the transmission line transmission can occur when the signal integrity problems. Meaning law semiconductor users Tongyang ask: for a group of bus (address, data, command) drives up to 4, 5 equipment (flash, SDRAM, etc.), in the PCB, bus in order to reach the equipment, such as the first connected to the SDRAM, flash...... A bus or star distribution, from somewhere separation, respectively connected to the equipment. These two kinds of methods in signal integrity, which is better?

In this regard, Bao Long Li pointed out that the routing topology of signal integrity effects, mainly reflected in each node signal arrival time inconsistent, signal reflection also reached a node at the moment is not consistent, so the resulting deterioration of signal quality. Generally speaking, the star topology, can through the control of several branches of the same length, the same signal transmission and reflection delay, achieve better signal quality. In the use of topology to take into account the signal between the topological nodes, working principle and wiring difficulty. Different buffer, for signal reflections are not consistent, so star topology and not very good solve the data and address bus is connected to the flash, and SDRAM latency, and can't ensure the signal quality; on the other hand, the high-speed signal generally between DSP and SDRAM communication and flash load rate is not high, so in the high speed simulation needs to ensure that the nodes of the effective work of the actual high-speed signal waveform, and no need to pay attention to the flash waveform; star topologies are compared in a daisy chain topology, routing is more difficult, and especially a large number of address data, use a star topology.

Effect of pad of high speed signal

In PCB, designed from the perspective of a hole is mainly composed of two parts: pad drilling and drilling around the middle. The famous fulonm engineers ask guests pad what influence on high speed signal in this regard, Li Baolong said: the pad has an effect on the high speed signal, the effects of similar devices on the device package. Detailed analysis of the signal from the IC came out, after bonding wires, pins, package, solder, solder joint to transmission line, all of this process will affect the quality of the signal. But the actual analysis, it is difficult to give specific parameters of pad, solder and pin. So with the parameters in IBIS model package they are summarized, of course, such analysis can be received at low frequencies, but for higher frequency signal with high accuracy of simulation is not accurate enough. Now is a trend to describe the Buffer properties of V-I, IBIS, V-T curve, SPICE model parameter description package.

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